The present invention relates generally to a low-GIDL (Gate-Induced Drain Leakage) current MOSFET device structure and a method of fabrication thereof.
As device geometries shrink, reliability problems due to Gate-Induced Drain Leakage (GIDL) current force operation at voltages which are lower than desired for best device performance.
The GIDL current results from the generation of electron-hole pairs in the surface drain depletion region of a field effect transistor along the area where the gate conductor overlaps the drain diffusion region, when the device is biased such that the drain potential is more positive (greater than +1 V) than the gate potential in an NMOSFET, and when the gate potential is more positive (greater than +1 V) than the drain potential in a PMOSFET.